In recent years, a semiconductor integrated circuit device having high integration with elements such as a transistor has been developed. In such device, a memory cell and others are laminated upward on a surface of a semiconductor wafer to produce a three-dimensional semiconductor integrated circuit device. As an example, there is a conventional technique which laminates a non-doped silicon film and a doped silicon film in multiple layers such that the memory cell becomes three-dimensional.
In such a conventional technique, if the elements become three-dimensional, the number of laminations of a laminated structure in the semiconductor integrated circuit device increases as compared with the existing semiconductor integrated circuit device which mainly includes planer-type elements.
In these circumstances, there are two major problems to be solved in the field of a semiconductor manufacturing process.
First, in the semiconductor manufacturing process, it is difficult to maintain and further enhance a good throughput. For example, the semiconductor integrated circuit device having three-dimensional integrated elements can be manufactured only by repeatedly performing processes of forming different films multiple times. In this case, the time required to manufacture one semiconductor integrated circuit device having three-dimensional elements becomes much longer than that of the semiconductor integrated circuit device integrating the planer-type elements.
Further, it is difficult to maintain a good surface roughness up to an upper layer of the laminated structure. If the number of film laminations increases, slight “disturbances” on a lower layer may affect its surface roughness, which will be amplified as it goes upward. As such, the surface roughness is likely to be more uneven towards the upper layer.